Instruction Description

ADDC
Operation:		Adds register S and the carry bit based on CC.
Description:		Adds register S and the carry bit together based on condition field CC. The result is placed in register D and the carry bit is set appropriately. Register field CC follows: CC Ci 00 0 01 1 10 C 11 C'
Instruction Format:		0 0 C C Sreg Dreg Bit addresses 7 6 5 4 3  2 1  0
Instruction Fields:		CC: The two-bit binary code for one of the conditions listed in the table. Sreg: Two-bit binary number specifying source register. Dreg: Two-bit binary number specifying destination (target) register.

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ADD
Operation:		Adds registers S, D, and the carry based on CC.
Description:		Adds registers S and D together with the carry bit based on condition field CC. The result is placed in register D and the carry bit is set appropriately. Register field CC follows: CC Ci 00 0 01 1 10 C 11 C'
Instruction Format:		0 1 C C Sreg Dreg Bit addresses 7 6 5 4 3  2 1  0
Instruction Fields:		CC: The two-bit binary code for one of the conditions listed in the table. Sreg: Two-bit binary number specifying source register. Dreg: Two-bit binary number specifying destination (target) register.

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SUBC
Operation:		Subtracts registers D, S, and the carry based on condition field CC.
Description:		Subtracts registers D minus S minus carry' based on condition field CC. The result is placed in register D and the carry bit is set appropriately. Register field CC follows: CC Ci 00 0 01 1 10 C 11 C'
Instruction Format:		1 0 C C Sreg Dreg Bit addresses 7 6 5 4 3  2 1  0
Instruction Fields:		CC: The two-bit binary code for one of the conditions listed in the table. Sreg: Two-bit binary number specifying source register. Dreg: Two-bit binary number specifying destination (target) register.

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Halt and I/O
Operation:		If halt bit set then halt program execution. If L bit set then read switches into specified register.
Description:		The Halt and I/O instruction can accomplish three tasks: When (H) is set, program execution is halted. When (L) is set, the switches are loaded into the specified destination register. This can be done either indepentendly or in conjunction with halting. Finally, the instruction has the implicit capability to provide a NOP command. When neither halt (H) nor I/O (L) are set, no operation is performed.
Instruction Format:		1 1 0 0 L H Dreg Bit addresses 7 6 5 4 3 2 1  0
Instruction Fields:		L: The L field specified to load when set to 1. H: The H field specified to halt program execution when set to 1. Dreg: Two-bit binary number specifying destination (target) register.

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Branch
Operation:		If (condition true) then branch to new address.
Description:		The branch instruction depends on the condition code CC. When CC evaluates to true the four-bit binary number is placed into the program counter. The table for CC follows: CC Ci 00 0 01 1 10 C 11 C'
Instruction Format:		1 1 C C ADDR Bit addresses 7 6 5 4 3 2 1 0
Instruction Fields:		CC: The two-bit binary code for one of the conditions listed in the table. ADDR: The four-bit binary address to be placed in the program counter.

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