OrCad Listings
The following listing is the supplied program which multiplies two four-bit unsigned numbers
together to get an eight-bit result
OrCAD PLD COMPILER V4.02 2/7/91 (Source file PRG1)
1 |gal22v10 2..5:(L3, L2, L1, L0), 23..16:(B7,B6,B5,B4,B3,B2,B1,B0)
2
3 ||high: L3,L2,L1,L0,B7,B6,B5,B4,B3,B2,B1,B0
4
5
6
7 | B7 = (L3'&L2')#(L2&L1')#(L3'&L2&L1&L0)#(L3&L2'&L1)
8 | B6 = (L2'&L1'&L0')#(L3&L2)#(L1&L0)#(L3&L2'&L1&L0)#(L3&L2'&L1&L0')
9 | B5 = (L2&L1&L0)#(L3&L2'&L1'&L0)
10 | B4 = (L3'&L1'&L0)#(L3'&L2&L0')#(L3&L2&L0)#(L3&L1&L0')
11 | B3 = (L3'&L1'&L0')#(L3'&L1&L0)#(L3'&L2&L0)#(L3&L2'&L1'&L0)
12 | B2 = (L2'&L0')#(L3'&L2&L1'&L0)#(L3&L1'&L0')#(L3&L2')#(L3'&L2'&L1&L0)
13 | B1 = (L3'&L2&L0)#(L2&L1'&L0')#(L3&L2')
14 | B0 = (L3'&L2'&L1'&L0')#(L3'&L2&L0)#(L3&L2'&L0)#(L3'&L2'&L1&L0)
RESOLVED EXPRESSIONS (Reduction 2)
Signal name Row Terms
B7 2 L3' L1'
3 L3' L0
4 L2' L1
5 L2 L1'
B6 11 L2' L1' L0'
12 L3 L2
13 L3 L1
14 L1 L0
B5 22 L3 L2' L1' L0
23 L2 L1 L0
B4 35 L3' L2 L0'
36 L3' L1' L0
37 L3 L2 L0
38 L3 L1 L0'
B3 50 L3 L2' L1' L0
51 L3' L2 L0
52 L3' L1' L0'
53 L3' L1 L0
B2 67 L3' L2 L1' L0
68 L3 L1' L0'
69 L3 L2'
70 L2' L1
71 L2' L0'
B1 84 L3' L2 L0
85 L2 L1' L0'
86 L3 L2'
B0 99 L3' L2' L1' L0'
100 L3' L2 L0
101 L3 L2' L0
102 L2' L1 L0
SIGNAL ASSIGNMENT
Rows
Pin Signal name Column -------------- Activity
Beg Avail Used
1. - 0 - - - (Clock)
2. L3 4 - - - High
3. L2 8 - - - High
4. L1 12 - - - High
5. L0 16 - - - High
6. - 20 - - -
7. - 24 - - -
8. - 28 - - -
9. - 32 - - -
10. - 36 - - -
11. - 40 - - -
13. - 42 - - -
14. - 38 122 9 0 (Registered)
15. - 34 111 11 0 (Registered)
16. B0 30 98 13 4 High (Three-state)
17. B1 26 83 15 3 High (Three-state)
18. B2 22 66 17 5 High (Three-state)
19. B3 18 49 17 4 High (Three-state)
20. B4 14 34 15 4 High (Three-state)
21. B5 10 21 13 2 High (Three-state)
22. B6 6 10 11 4 High (Three-state)
23. B7 2 1 9 4 High (Three-state)
25. - - 0 1 0
26. - - 131 1 0
---- ----
132 30 (23%)
I200 No fatal errors found in source code.
I201 No warnings.
OrCAD PLD
Type: PAL22V10
QP24* QF5828* QV1024*
F0*
L0044 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0088 11 11 10 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0132 11 11 10 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0176 11 11 11 11 10 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0220 11 11 11 11 01 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0440 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0484 11 11 11 11 10 11 10 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0528 11 11 01 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0572 11 11 01 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0616 11 11 11 11 11 11 01 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0924 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0968 11 11 01 11 10 11 10 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1012 11 11 11 11 01 11 01 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1496 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1540 11 11 10 11 01 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1584 11 11 10 11 11 11 10 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1628 11 11 01 11 01 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1672 11 11 01 11 11 11 01 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2156 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2200 11 11 01 11 10 11 10 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2244 11 11 10 11 01 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2288 11 11 10 11 11 11 10 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2332 11 11 10 11 11 11 01 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2904 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2948 11 11 10 11 01 11 10 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2992 11 11 01 11 11 11 10 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3036 11 11 01 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3080 11 11 11 11 10 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3124 11 11 11 11 10 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3652 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3696 11 11 10 11 01 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3740 11 11 11 11 01 11 10 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3784 11 11 01 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4312 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4356 11 11 10 11 10 11 10 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4400 11 11 10 11 01 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4444 11 11 01 11 10 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4488 11 11 11 11 10 11 01 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L5808 11 11 11 11 11 11 11 11 11 11 *
CCDD3*
I202 12/2/93 4:18 pm (Thursday)
I203 Memory utilization 2607/17818 (15%)
I204 Elapsed time 11 seconds
The following listing is the second program which reads a number from the switches
and then rotates this through the LEDs.
OrCAD PLD COMPILER V4.02 2/7/91 (Source file PRG2.PLD)
1 |gal22v10 in: (L3, L2, L1, L0), io: (B7,B6,B5,B4,B3,B2,B1,B0)
2
3 |high: L3,L2,L1,L0,B7,B6,B5,B4,B3,B2,B1,B0
4
5 || This is the 2nd test program to load the lights and rotate them.
6
7 | B7 = L1'
8 | B6 = (L1&L0)'
9 | B5 = L1&L0
10 | B4 = L2
11 | B3 = L0'&L1'&L2'&L3'
12 | B2 = L1
13 | B1 = 0
14 | B0 = 1
RESOLVED EXPRESSIONS (Reduction 2)
Signal name Row Terms
B7 2 L1'
B6 11 L1'
12 L0'
B5 22 L1 L0
B4 35 L2
B3 50 L3' L2' L1' L0'
B2 67 L1
B1 84 0
B0 99 1
SIGNAL ASSIGNMENT
Rows
Pin Signal name Column -------------- Activity
Beg Avail Used
1. - 0 - - - (Clock)
2. L3 4 - - - High
3. L2 8 - - - High
4. L1 12 - - - High
5. L0 16 - - - High
6. - 20 - - -
7. - 24 - - -
8. - 28 - - -
9. - 32 - - -
10. - 36 - - -
11. - 40 - - -
13. - 42 - - -
14. - 38 122 9 0 (Registered)
15. - 34 111 11 0 (Registered)
16. B0 30 98 13 1 High (Three-state)
17. B1 26 83 15 1 High (Three-state)
18. B2 22 66 17 1 High (Three-state)
19. B3 18 49 17 1 High (Three-state)
20. B4 14 34 15 1 High (Three-state)
21. B5 10 21 13 1 High (Three-state)
22. B6 6 10 11 2 High (Three-state)
23. B7 2 1 9 1 High (Three-state)
25. - - 0 1 0
26. - - 131 1 0
---- ----
132 9 (7%)
I200 No fatal errors found in source code.
I201 No warnings.
OrCAD PLD
Type: PAL22V10
QP24* QF5828* QV1024*
F0*
L0044 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0088 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0440 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0484 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0528 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0924 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0968 11 11 11 11 11 11 01 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1496 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1540 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2156 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2200 11 11 10 11 10 11 10 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2904 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2948 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3652 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4312 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4356 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L5808 11 11 11 11 11 11 11 11 11 11 *
C592B*
I202 11/24/93 9:44 pm (Wednesday)
I203 Memory utilization 1814/18330 (10%)
I204 Elapsed time 8 seconds
The following listing is the PC-incrementing logic. This either adds one
to the PC or gives it the new address from a branch instruction.
OrCAD PLD COMPILER V4.02 2/7/91 (Source file PC.PLD)
1 |gal22v10
2 || in: (Bin[3..0], Ain[3..0], bPrayer, OurReset),
3 || io: (Aout[3..0]),
4 || clock: (CLK)
5 | 1: aClk, 2..5:Bin[3..0], 6..9: Ain[3..0], 10: bPrayer, 20..23: Aout[0..3],
19: aClkNot,
6 | 11: OurReset
7 || 19: aClkNot
8
9 || conditioning: CLK \\ Aout[3..0]
10
11 || Aout[3] = (bPrayer & (Bin[3]))
12 || Aout[2] = (bPrayer & (Bin[2]))
13 || Aout[1] = (bPrayer & (Bin[1]))
14 || Aout[0] = (bPrayer & (Bin[0]))
15
16 | Aout[3..0] = (bPrayer & Bin[3..0]) & OurReset'
17 | Aout[3..0] = (bPrayer' & (Ain[3..0]+1)) & OurReset'
18
19 | aClkNot = aClk'
RESOLVED EXPRESSIONS (Reduction 2)
Signal name Row Terms
Aout3 2 Ain3' Ain2 Ain1 Ain0 bPrayer' OurReset'
3 Ain3 Ain2' bPrayer' OurReset'
4 Ain3 Ain1' bPrayer' OurReset'
5 Ain3 Ain0' bPrayer' OurReset'
6 Bin3 bPrayer OurReset'
Aout2 11 Ain2' Ain1 Ain0 bPrayer' OurReset'
12 Ain2 Ain1' bPrayer' OurReset'
13 Ain2 Ain0' bPrayer' OurReset'
14 Bin2 bPrayer OurReset'
Aout1 22 Ain1' Ain0 bPrayer' OurReset'
23 Ain1 Ain0' bPrayer' OurReset'
24 Bin1 bPrayer OurReset'
Aout0 35 Bin0 bPrayer OurReset'
36 Ain0' bPrayer' OurReset'
aClkNot 50 aClk'
SIGNAL ASSIGNMENT
Rows
Pin Signal name Column -------------- Activity
Beg Avail Used
1. aClk 0 - - - High (Clock)
2. Bin3 4 - - - High
3. Bin2 8 - - - High
4. Bin1 12 - - - High
5. Bin0 16 - - - High
6. Ain3 20 - - - High
7. Ain2 24 - - - High
8. Ain1 28 - - - High
9. Ain0 32 - - - High
10. bPrayer 36 - - - High
11. OurReset 40 - - - High
13. - 42 - - -
14. - 38 122 9 0 (Registered)
15. - 34 111 11 0 (Registered)
16. - 30 98 13 0 (Registered)
17. - 26 83 15 0 (Registered)
18. - 22 66 17 0 (Registered)
19. aClkNot 18 49 17 1 High (Three-state)
20. Aout0 14 34 15 2 High (Three-state)
21. Aout1 10 21 13 3 High (Three-state)
22. Aout2 6 10 11 4 High (Three-state)
23. Aout3 2 1 9 5 High (Three-state)
25. - - 0 1 0
26. - - 131 1 0
---- ----
132 15 (11%)
I200 No fatal errors found in source code.
I201 No warnings.
OrCAD PLD
Type: PAL22V10
QP24* QF5828* QV1024*
F0*
L0044 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0088 11 11 11 11 11 11 11 11 11 11 10 11 01 11 01 11 01 11 10 11 10 11 *
L0132 11 11 11 11 11 11 11 11 11 11 01 11 10 11 11 11 11 11 10 11 10 11 *
L0176 11 11 11 11 11 11 11 11 11 11 01 11 11 11 10 11 11 11 10 11 10 11 *
L0220 11 11 11 11 11 11 11 11 11 11 01 11 11 11 11 11 10 11 10 11 10 11 *
L0264 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 10 11 *
L0440 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0484 11 11 11 11 11 11 11 11 11 11 11 11 10 11 01 11 01 11 10 11 10 11 *
L0528 11 11 11 11 11 11 11 11 11 11 11 11 01 11 10 11 11 11 10 11 10 11 *
L0572 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 10 11 10 11 10 11 *
L0616 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 10 11 *
L0924 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0968 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 01 11 10 11 10 11 *
L1012 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 10 11 10 11 10 11 *
L1056 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 01 11 10 11 *
L1496 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1540 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 01 11 10 11 *
L1584 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 10 11 10 11 *
L2156 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2200 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L5808 11 11 11 11 11 11 11 11 11 11 *
C6B76*
I202 12/1/93 10:05 am (Wednesday)
I203 Memory utilization 1904/17818 (11%)
I204 Elapsed time 10 seconds
The following listing is a transparent latch used on Earth to latch the inputs
to the ALU. This prevents feedback to the ALU when the answer is written
back into the destination register.
OrCAD PLD COMPILER V4.02 2/7/91 (Source file TRNSLTCH.PLD)
1 |gal22v10
2
3 Transparent Latch Inputs D
4 | 2..10: (D[8..0]), 11: (L),
5
6 Transparent Latch Outputs Q
7 | 15..23: (Q[0..8])
8
9 |Q[8..0] = (L&D[8..0]) # (Q[8..0] & (L&D[8..0]')')
RESOLVED EXPRESSIONS (Reduction 2)
Signal name Row Terms
Q8 2 D8 L
3 L' Q8
Q7 11 D7 L
12 L' Q7
Q6 22 D6 L
23 L' Q6
Q5 35 D5 L
36 L' Q5
Q4 50 D4 L
51 L' Q4
Q3 67 D3 L
68 L' Q3
Q2 84 D2 L
85 L' Q2
Q1 99 D1 L
100 L' Q1
Q0 112 D0 L
113 L' Q0
SIGNAL ASSIGNMENT
Rows
Pin Signal name Column -------------- Activity
Beg Avail Used
1. - 0 - - - (Clock)
2. D8 4 - - - High
3. D7 8 - - - High
4. D6 12 - - - High
5. D5 16 - - - High
6. D4 20 - - - High
7. D3 24 - - - High
8. D2 28 - - - High
9. D1 32 - - - High
10. D0 36 - - - High
11. L 40 - - - High
13. - 42 - - -
14. - 38 122 9 0 (Registered)
15. Q0 34 111 11 2 High (Three-state)
16. Q1 30 98 13 2 High (Three-state)
17. Q2 26 83 15 2 High (Three-state)
18. Q3 22 66 17 2 High (Three-state)
19. Q4 18 49 17 2 High (Three-state)
20. Q5 14 34 15 2 High (Three-state)
21. Q6 10 21 13 2 High (Three-state)
22. Q7 6 10 11 2 High (Three-state)
23. Q8 2 1 9 2 High (Three-state)
25. - - 0 1 0
26. - - 131 1 0
---- ----
132 18 (14%)
I200 No fatal errors found in source code.
I201 No warnings.
OrCAD PLD
Type: PAL22V10
QP24* QF5828* QV1024*
F0*
L0044 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0088 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 *
L0132 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 *
L0440 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0484 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 *
L0528 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 *
L0924 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0968 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 *
L1012 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 *
L1496 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1540 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 01 11 *
L1584 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 10 11 *
L2156 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2200 11 11 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 01 11 *
L2244 11 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 10 11 *
L2904 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2948 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 01 11 *
L2992 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 10 11 *
L3652 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3696 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 11 11 01 11 *
L3740 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 10 11 *
L4312 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4356 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 01 11 *
L4400 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 11 10 11 *
L4884 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4928 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 01 11 *
L4972 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 10 11 *
L5808 11 11 11 11 11 11 11 11 11 11 *
C92AC*
I202 11/29/93 7:06 pm (Monday)
I203 Memory utilization 1912/17818 (11%)
I204 Elapsed time 10 seconds
The following listing acts as a switch in the Earth circuitry to either
pass the output from the ALU or the inputs from the user switches.
OrCAD PLD COMPILER V4.02 2/7/91 (Source file TRI)
1 |gal22v10
2 || This acts as a switch and either passes the switches or the alu output.
3 | 2..5:Switch[3..0], 6..9: Alu[3..0], 10: TriSel, 20..23: Aout[0..3]
4
5 | Aout[3..0] = (TriSel' & (Switch[3..0]))
6 | Aout[3..0] = (TriSel & (Alu[3..0]))
RESOLVED EXPRESSIONS (Reduction 2)
Signal name Row Terms
Aout3 2 Switch3 TriSel'
3 Alu3 TriSel
Aout2 11 Switch2 TriSel'
12 Alu2 TriSel
Aout1 22 Switch1 TriSel'
23 Alu1 TriSel
Aout0 35 Switch0 TriSel'
36 Alu0 TriSel
SIGNAL ASSIGNMENT
Rows
Pin Signal name Column -------------- Activity
Beg Avail Used
1. - 0 - - - (Clock)
2. Switch3 4 - - - High
3. Switch2 8 - - - High
4. Switch1 12 - - - High
5. Switch0 16 - - - High
6. Alu3 20 - - - High
7. Alu2 24 - - - High
8. Alu1 28 - - - High
9. Alu0 32 - - - High
10. TriSel 36 - - - High
11. - 40 - - -
13. - 42 - - -
14. - 38 122 9 0 (Registered)
15. - 34 111 11 0 (Registered)
16. - 30 98 13 0 (Registered)
17. - 26 83 15 0 (Registered)
18. - 22 66 17 0 (Registered)
19. - 18 49 17 0 (Registered)
20. Aout0 14 34 15 2 High (Three-state)
21. Aout1 10 21 13 2 High (Three-state)
22. Aout2 6 10 11 2 High (Three-state)
23. Aout3 2 1 9 2 High (Three-state)
25. - - 0 1 0
26. - - 131 1 0
---- ----
132 8 (6%)
I200 No fatal errors found in source code.
I201 No warnings.
OrCAD PLD
Type: PAL22V10
QP24* QF5828* QV1024*
F0*
L0044 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0088 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 11 11 *
L0132 11 11 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 01 11 11 11 *
L0440 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0484 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 11 11 *
L0528 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 11 11 01 11 11 11 *
L0924 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0968 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 10 11 11 11 *
L1012 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 01 11 11 11 *
L1496 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1540 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 10 11 11 11 *
L1584 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 01 11 11 11 *
L5808 11 11 11 11 11 11 11 11 11 11 *
C4321*
I202 11/29/93 12:51 am (Monday)
I203 Memory utilization 1754/17818 (10%)
I204 Elapsed time 7 seconds
The following listing is the combinational logic used to control the
components of Earth. In a system using micro code or multiple states
per instruction, this would be a finite state machine.
OrCAD PLD COMPILER V4.02 2/7/91 (Source file EARTH.PLD)
1 |gal22v10
2
3 FMS Inputs.
4
5 | 2..9:(I[7..0]),10:(Carry),
6 | 11:(WriteClock),
7 || clock: (CLK), | pin 1
8
9 FMS Outputs.
10
11 | 16:(Cin),
12 | 20:(CWrite),
13 | 17:(WriteEn),
14 | 21:(TriState),
15 | 18:(SegLatch),
16 | 19:(LEDLatch),
17 | 14:(Hprayer),
18 | 15:(Bprayer)
19
20
21 || conditioning: CLK // Cin,TriState,Hprayer,Bprayer
22 || conditioning: CLK' // WriteEn,SegLatch,LEDLatch
23
24
25
26 || Cin = ((I[5]' & I[4]) # (Carry' & I[4]) # (Carry & I[5] & I[4]')) ## I7
27 | Cin = ((I[5]' & I[4]) #
28 | (Carry' & I[5] & I[4]) #
29 | (Carry & I[5] & I[4]'))|sdfsdf ## I[7]
30 | CWrite = (I[7] & I[6])' & WriteClock'
31
32 | WriteEn= ( ((I[7] & I[6])' # (I[7] & I[6] & I[5]' & I[4]' & I[3])) & WriteClock'
)'
33 TriState = 1 means ALU; Happens on a Halt/IO
34 TriState = 0 means switches
35 | TriState = (I[7] & I[6] & I[5]' & I[4]' & I[3])'
36
37 | SegLatch = (I[7] & I[6] & I[5]' & I[4] )' &
38 | (I[7] & I[6] & I[5] & I[4]')' &
39 | (I[7] & I[6] & I[5] & I[4] )'
40
41 | LEDLatch = (I[7] & I[6] & I[5]' & I[4]')
42
43 | Hprayer = I[7] & I[6] & I[5]' & I[4]' & I[2]
44 || Bprayer = I[7] & I[6] & (I[5]' & I[4]')'
45 | Bprayer = (I[7] & I[6] & I[5]' & I[4]) #
46 | (I[7] & I[6] & I[5] & I[4]' & Carry) #
47 | (I[7] & I[6] & I[5] & I[4] & Carry')
RESOLVED EXPRESSIONS (Reduction 4)
Signal name Row Terms
Cin 99 I5 I4' Carry
100 I5 I4 Carry'
101 I5' I4
CWrite 35 I7' WriteClock'
36 I6' WriteClock'
WriteEn 84 I7 I6 I5
85 I7 I6 I4
86 I7 I6 I3'
87 WriteClock
TriState 22 I7'
23 I6'
24 I5
25 I4
26 I3'
SegLatch 67 I7' I6'
68 I5' I4'
69 I7'
70 I6'
LEDLatch 50 I7 I6 I5' I4'
Hprayer 123 I7 I6 I5' I4' I2
Bprayer 112 I7 I6 I5 I4' Carry
113 I7 I6 I5 I4 Carry'
114 I7 I6 I5' I4
SIGNAL ASSIGNMENT
Rows
Pin Signal name Column -------------- Activity
Beg Avail Used
1. - 0 - - - (Clock)
2. I7 4 - - - High
3. I6 8 - - - High
4. I5 12 - - - High
5. I4 16 - - - High
6. I3 20 - - - High
7. I2 24 - - - High
8. I1 28 - - - High
9. I0 32 - - - High
10. Carry 36 - - - High
11. WriteClock 40 - - - High
13. - 42 - - -
14. Hprayer 38 122 9 1 High (Three-state)
15. Bprayer 34 111 11 3 High (Three-state)
16. Cin 30 98 13 3 High (Three-state)
17. WriteEn 26 83 15 4 High (Three-state)
18. SegLatch 22 66 17 4 High (Three-state)
19. LEDLatch 18 49 17 1 High (Three-state)
20. CWrite 14 34 15 2 High (Three-state)
21. TriState 10 21 13 5 High (Three-state)
22. - 6 10 11 0 (Registered)
23. - 2 1 9 0 (Registered)
25. - - 0 1 0
26. - - 131 1 0
---- ----
132 23 (17%)
W320 Signal I0 is not used in the final equations.
W320 Signal I1 is not used in the final equations.
I200 No fatal errors found in source code.
I201 Two warnings.
OrCAD PLD
Type: PAL22V10
QP24* QF5828* QV1024*
F0*
L0924 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0968 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1012 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1056 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1100 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1144 11 11 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 *
L1496 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1540 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 *
L1584 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 *
L2156 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2200 11 11 01 11 01 11 10 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2904 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2948 11 11 10 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2992 11 11 11 11 11 11 10 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3036 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3080 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3652 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3696 11 11 01 11 01 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3740 11 11 01 11 01 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3784 11 11 01 11 01 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 *
L3828 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 *
L4312 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4356 11 11 11 11 11 11 01 11 10 11 11 11 11 11 11 11 11 11 01 11 11 11 *
L4400 11 11 11 11 11 11 01 11 01 11 11 11 11 11 11 11 11 11 10 11 11 11 *
L4444 11 11 11 11 11 11 10 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4884 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4928 11 11 01 11 01 11 01 11 10 11 11 11 11 11 11 11 11 11 01 11 11 11 *
L4972 11 11 01 11 01 11 01 11 01 11 11 11 11 11 11 11 11 11 10 11 11 11 *
L5016 11 11 01 11 01 11 10 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L5368 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L5412 11 11 01 11 01 11 10 11 10 11 11 11 01 11 11 11 11 11 11 11 11 11 *
L5808 11 11 11 11 11 11 11 11 11 11 *
CA89D*
I202 11/30/93 8:23 pm (Tuesday)
I203 Memory utilization 3016/19188 (16%)
I204 Elapsed time 12 seconds
The following listing is the combinational logic used in the ALU.
OrCAD PLD COMPILER V4.02 2/7/91 (Source file ALU2.PLD)
1 |gal22v10
2 | 2..11:(S[3..0],D[3..0],C[0],P[1]),13:(P[0]),
3 | 15:(R[0]),18:(R[1]),16:(R[2]),17:(R[3]),
4 | 14:(C[1]),19:(C[2]),20:(C[3]),21:(C[4])
5
6
7
8 |i=3..0:
9 |{ dd[i] = (D[i] & P[0]) # (D[i] & P[1])
10 | ss[i] = S[i] ## P[1] }
11 || cc[0] = C[0] ## P[1]
12
13 | R[0] = ss[0] ## dd[0] ## C[0]
14 | C[1] = ( (ss[0] ## dd[0]) & C[0] ) # (ss[0] & dd[0])
15
16 | R[1] = ss[1] ## dd[1] ## C[1]
17 | C[2] = ( (ss[1] ## dd[1])&(ss[0] ## dd[0])&C[0] ) #
18 | ( (ss[1] ## dd[1])& ss[0]&dd[0] ) #
19 | ( (ss[1] & dd[1]) )
20
21 | R[2] = ss[2] ## dd[2] ## C[2]
22 | C[3] = ( (ss[2] ## dd[2])&(ss[1] ## dd[1])&C[1] ) #
23 | ( (ss[2] ## dd[2])& ss[1]&dd[1] ) #
24 | ( (ss[2] & dd[2]) )
25
26 | R[3] = ss[3] ## dd[3] ## C[3]
27 | C[4] = ( (ss[3] ## dd[3]) & C[3] ) # (ss[3] & dd[3])
28
29 |Vectors:
30 | { Display S[3..0], D[3..0], C[0], P[1..0],C[4],R[3..0], C[3..1]
31 |TEST S[3..0]; D[3..0]; C[0]; P1 = 0; P0 = 1
32 | END }
33
34
35
36
RESOLVED EXPRESSIONS (Reduction 2)
Signal name Row Terms
R0 112 S0' D0 C0' P1' P0
113 S0 D0 C0 P1' P0
114 S0' D0' C0' P1
115 S0' D0' C0 P1'
116 S0' D0 C0 P1
117 S0' D0 C0 P0'
118 S0 D0' C0' P1'
119 S0 D0' C0 P1
120 S0 D0 C0' P1
121 S0 D0 C0' P0'
C1 123 S0 D0 P1' P0
124 S0' D0 P1
125 S0' C0 P1
126 S0 D0 C0
127 S0 C0 P1'
128 D0 C0 P0
R1 67 S1' D1 P1' P0 C1'
68 S1 D1 P1' P0 C1
69 S1' D1' P1' C1
70 S1' D1' P1 C1'
71 S1' D1 P1 C1
72 S1' D1 P0' C1
73 S1 D1' P1' C1'
74 S1 D1' P1 C1
75 S1 D1 P1 C1'
76 S1 D1 P0' C1'
C2 50 S1 S0 D1 D0 C0
51 S1 S0 D0 P1' P0
52 S1 D0 C0 P1' P0
53 S0 D1 D0 P1' P0
54 S0 D1 C0 P1' P0
55 S1' S0' D0 P1
56 S1' S0' C0 P1
57 S1' D0 C0 P1
58 S1 S0 C0 P1'
59 S1 D1 P1' P0
60 S0' D1 D0 P1
61 S0' D1 C0 P1
62 D1 D0 C0 P0
63 S1' D1 P1
R2 99 S2' D2 P1' P0 C2'
100 S2 D2 P1' P0 C2
101 S2' D2' P1' C2
102 S2' D2' P1 C2'
103 S2' D2 P1 C2
104 S2' D2 P0' C2
105 S2 D2' P1' C2'
106 S2 D2' P1 C2
107 S2 D2 P1 C2'
108 S2 D2 P0' C2'
C3 35 S2 S1 D2 D1 C1
36 S2 S1 D1 P1' P0
37 S2 D1 P1' P0 C1
38 S1 D2 D1 P1' P0
39 S1 D2 P1' P0 C1
40 S2' S1' D1 P1
41 S2' S1' P1 C1
42 S2' D1 P1 C1
43 S2 S1 P1' C1
44 S2 D2 P1' P0
45 S1' D2 D1 P1
46 S1' D2 P1 C1
47 D2 D1 P0 C1
48 S2' D2 P1
R3 84 S3' D3 P1' P0 C3'
85 S3 D3 P1' P0 C3
86 S3' D3' P1' C3
87 S3' D3' P1 C3'
88 S3' D3 P1 C3
89 S3' D3 P0' C3
90 S3 D3' P1' C3'
91 S3 D3' P1 C3
92 S3 D3 P1 C3'
93 S3 D3 P0' C3'
C4 22 S3 D3 P1' P0
23 S3' D3 P1
24 S3' P1 C3
25 S3 D3 C3
26 S3 P1' C3
27 D3 P0 C3
SIGNAL ASSIGNMENT
Rows
Pin Signal name Column -------------- Activity
Beg Avail Used
1. - 0 - - - (Clock)
2. S3 4 - - - High
3. S2 8 - - - High
4. S1 12 - - - High
5. S0 16 - - - High
6. D3 20 - - - High
7. D2 24 - - - High
8. D1 28 - - - High
9. D0 32 - - - High
10. C0 36 - - - High
11. P1 40 - - - High
13. P0 42 - - - High
14. C1 38 122 9 6 High (Three-state)
15. R0 34 111 11 10 High (Three-state)
16. R2 30 98 13 10 High (Three-state)
17. R3 26 83 15 10 High (Three-state)
18. R1 22 66 17 10 High (Three-state)
19. C2 18 49 17 14 High (Three-state)
20. C3 14 34 15 14 High (Three-state)
21. C4 10 21 13 6 High (Three-state)
22. - 6 10 11 0 (Registered)
23. - 2 1 9 0 (Registered)
25. - - 0 1 0
26. - - 131 1 0
---- ----
132 80 (61%)
I200 No fatal errors found in source code.
I201 No warnings.
OrCAD PLD
Type: PAL22V10
*
QP24* QF5828* QV1024*
F0*
L0924 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0968 11 11 01 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 10 01 *
L1012 11 11 10 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 01 11 *
L1056 11 11 10 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 01 11 *
L1100 11 11 01 11 11 11 11 01 11 11 01 11 11 11 11 11 11 11 11 11 11 11 *
L1144 11 11 01 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 10 11 *
L1188 11 11 11 11 11 11 11 01 11 11 01 11 11 11 11 11 11 11 11 11 11 01 *
L1496 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1540 11 11 11 11 01 11 01 11 11 11 11 11 01 11 01 11 11 11 11 01 11 11 *
L1584 11 11 11 11 01 11 01 11 11 11 11 11 11 11 01 11 11 11 11 11 10 01 *
L1628 11 11 11 11 01 11 11 11 11 11 11 11 11 11 01 11 11 11 11 01 10 01 *
L1672 11 11 11 11 11 11 01 11 11 11 11 11 01 11 01 11 11 11 11 11 10 01 *
L1716 11 11 11 11 11 11 01 11 11 11 11 11 01 11 11 11 11 11 11 01 10 01 *
L1760 11 11 11 11 10 11 10 11 11 11 11 11 11 11 01 11 11 11 11 11 01 11 *
L1804 11 11 11 11 10 11 10 11 11 11 11 11 11 11 11 11 11 11 11 01 01 11 *
L1848 11 11 11 11 10 11 11 11 11 11 11 11 11 11 01 11 11 11 11 01 01 11 *
L1892 11 11 11 11 01 11 01 11 11 11 11 11 11 11 11 11 11 11 11 01 10 11 *
L1936 11 11 11 11 01 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 10 01 *
L1980 11 11 11 11 11 11 10 11 11 11 11 11 01 11 01 11 11 11 11 11 01 11 *
L2024 11 11 11 11 11 11 10 11 11 11 11 11 01 11 11 11 11 11 11 01 01 11 *
L2068 11 11 11 11 11 11 11 11 11 11 11 11 01 11 01 11 11 11 11 01 11 01 *
L2112 11 11 11 11 10 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 01 11 *
L2156 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2200 11 11 11 11 11 11 01 11 01 11 11 11 11 11 01 11 01 11 01 11 11 11 *
L2244 11 11 11 11 11 11 01 11 01 11 11 11 11 11 11 11 01 11 11 11 10 01 *
L2288 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 01 11 01 11 10 01 *
L2332 11 11 11 11 11 11 11 11 01 11 11 11 11 11 01 11 01 11 11 11 10 01 *
L2376 11 11 11 11 11 11 11 11 01 11 11 11 11 11 01 11 11 11 01 11 10 01 *
L2420 11 11 11 11 11 11 10 11 10 11 11 11 11 11 11 11 01 11 11 11 01 11 *
L2464 11 11 11 11 11 11 10 11 10 11 11 11 11 11 11 11 11 11 01 11 01 11 *
L2508 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 01 11 01 11 01 11 *
L2552 11 11 11 11 11 11 01 11 01 11 11 11 11 11 11 11 11 11 01 11 10 11 *
L2596 11 11 11 11 11 11 01 11 11 11 11 11 11 11 01 11 11 11 11 11 10 01 *
L2640 11 11 11 11 11 11 11 11 10 11 11 11 11 11 01 11 01 11 11 11 01 11 *
L2684 11 11 11 11 11 11 11 11 10 11 11 11 11 11 01 11 11 11 01 11 01 11 *
L2728 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 01 11 01 11 11 01 *
L2772 11 11 11 11 11 11 10 11 11 11 11 11 11 11 01 11 11 11 11 11 01 11 *
L2904 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2948 11 11 11 11 11 11 10 11 11 11 11 11 11 11 01 11 11 11 11 10 10 01 *
L2992 11 11 11 11 11 11 01 11 11 11 11 11 11 11 01 11 11 11 11 01 10 01 *
L3036 11 11 11 11 11 11 10 11 11 11 11 11 11 11 10 11 11 11 11 01 10 11 *
L3080 11 11 11 11 11 11 10 11 11 11 11 11 11 11 10 11 11 11 11 10 01 11 *
L3124 11 11 11 11 11 11 10 11 11 11 11 11 11 11 01 11 11 11 11 01 01 11 *
L3168 11 11 11 11 11 11 10 11 11 11 11 11 11 11 01 11 11 11 11 01 11 10 *
L3212 11 11 11 11 11 11 01 11 11 11 11 11 11 11 10 11 11 11 11 10 10 11 *
L3256 11 11 11 11 11 11 01 11 11 11 11 11 11 11 10 11 11 11 11 01 01 11 *
L3300 11 11 11 11 11 11 01 11 11 11 11 11 11 11 01 11 11 11 11 10 01 11 *
L3344 11 11 11 11 11 11 01 11 11 11 11 11 11 11 01 11 11 11 11 10 11 10 *
L3652 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3696 11 11 10 11 11 11 11 10 11 11 01 11 11 11 11 11 11 11 11 11 10 01 *
L3740 11 11 01 11 11 11 11 01 11 11 01 11 11 11 11 11 11 11 11 11 10 01 *
L3784 11 11 10 11 11 11 11 01 11 11 10 11 11 11 11 11 11 11 11 11 10 11 *
L3828 11 11 10 11 11 11 11 10 11 11 10 11 11 11 11 11 11 11 11 11 01 11 *
L3872 11 11 10 11 11 11 11 01 11 11 01 11 11 11 11 11 11 11 11 11 01 11 *
L3916 11 11 10 11 11 11 11 01 11 11 01 11 11 11 11 11 11 11 11 11 11 10 *
L3960 11 11 01 11 11 11 11 10 11 11 10 11 11 11 11 11 11 11 11 11 10 11 *
L4004 11 11 01 11 11 11 11 01 11 11 10 11 11 11 11 11 11 11 11 11 01 11 *
L4048 11 11 01 11 11 11 11 10 11 11 01 11 11 11 11 11 11 11 11 11 01 11 *
L4092 11 11 01 11 11 11 11 10 11 11 01 11 11 11 11 11 11 11 11 11 11 10 *
L4312 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4356 11 11 11 11 10 11 11 11 11 10 11 11 01 11 11 11 11 11 11 11 10 01 *
L4400 11 11 11 11 01 11 11 11 11 01 11 11 01 11 11 11 11 11 11 11 10 01 *
L4444 11 11 11 11 10 11 11 11 11 01 11 11 10 11 11 11 11 11 11 11 10 11 *
L4488 11 11 11 11 10 11 11 11 11 10 11 11 10 11 11 11 11 11 11 11 01 11 *
L4532 11 11 11 11 10 11 11 11 11 01 11 11 01 11 11 11 11 11 11 11 01 11 *
L4576 11 11 11 11 10 11 11 11 11 01 11 11 01 11 11 11 11 11 11 11 11 10 *
L4620 11 11 11 11 01 11 11 11 11 10 11 11 10 11 11 11 11 11 11 11 10 11 *
L4664 11 11 11 11 01 11 11 11 11 01 11 11 10 11 11 11 11 11 11 11 01 11 *
L4708 11 11 11 11 01 11 11 11 11 10 11 11 01 11 11 11 11 11 11 11 01 11 *
L4752 11 11 11 11 01 11 11 11 11 10 11 11 01 11 11 11 11 11 11 11 11 10 *
L4884 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4928 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 01 11 10 11 10 01 *
L4972 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 01 11 01 11 10 01 *
L5016 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 10 11 10 11 01 11 *
L5060 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 10 11 01 11 10 11 *
L5104 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 01 11 01 11 01 11 *
L5148 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 01 11 01 11 11 10 *
L5192 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 10 11 10 11 10 11 *
L5236 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 10 11 01 11 01 11 *
L5280 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 01 11 10 11 01 11 *
L5324 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 01 11 10 11 11 10 *
L5368 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L5412 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 01 11 11 11 10 01 *
L5456 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 01 11 11 11 01 11 *
L5500 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 01 11 01 11 *
L5544 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 01 11 01 11 11 11 *
L5588 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 01 11 10 11 *
L5632 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 01 11 11 01 *
L5808 11 11 11 11 11 11 11 11 11 11 *
CCC34*
I202 12/2/93 3:48 pm (Thursday)
I203 Memory utilization 9746/17818 (55%)
I204 Elapsed time 38 seconds